Applied Materials and Intel deepen chip R&D tie-up at EPIC Centre

Applied Materials and Intel have announced an expanded research collaboration targeting next-generation chipmaking technologies, with joint teams working across both Applied's new EPIC (Equipment and Process Innovation and Commercialisation) Centre in Silicon Valley and Intel's R&D campus in Hillsboro, Oregon. The partnership, rooted in decades of joint work on process development, is now focused explicitly on the materials engineering and packaging advances required for AI-oriented silicon.

The scope covers front-end and back-end-of-line development, including advanced logic nodes for AI workloads, interconnect scaling and, notably, Intel's Foveros-based 3D stacking packaging platform. Applied and Intel say the Foveros work is aimed at higher interconnect density, improved power delivery and better thermal performance for high-performance compute platforms designed to handle agentic AI workloads.

The EPIC Centre

Applied's EPIC facility is scheduled to become operationally ready before year-end and is described by the company as purpose-built to compress the path from early-stage research to high-volume manufacturing. The model is one of co-location: chipmakers gain earlier access to Applied's R&D portfolio and faster learning cycles, while Applied gains what it calls "multi-node visibility" to guide its own investment decisions.

Intel chief executive Lip-Bu Tan said the partnership reflects the pressure AI demand is placing on the semiconductor supply chain. "The demand for AI computing is driving the need for major advances in performance, power efficiency, and packaging," he said. "Applied Materials is an important partner, and we look forward to expanding our work together at the EPIC Center to help accelerate the path from the lab to high-volume manufacturing in the United States."

The reference to US-based high-volume manufacturing is not incidental. Intel's foundry ambitions depend heavily on domestic production capacity, and the collaboration fits within a broader political and industrial context in which the CHIPS and Science Act has directed tens of billions of dollars toward on-shore semiconductor R&D and fabrication.

Market context

The collaboration reflects a structural shift in how the semiconductor industry approaches process development. As transistor scaling approaches physical limits at leading nodes, progress increasingly depends on materials innovation, novel device architectures and heterogeneous integration rather than straightforward lithographic shrinks. That complexity is drawing equipment makers and chipmakers into deeper joint development arrangements earlier in the design cycle.

Applied Materials is the dominant supplier of deposition, etch and thermal equipment globally, and its EPIC model mirrors co-innovation facilities that ASML, Lam Research and others have operated for years, though Applied positions EPIC as more deeply integrated with customer roadmaps than a standard applications lab.

For Intel Foundry, which is competing for advanced-node customers against TSMC and Samsung, demonstrating tight ecosystem partnerships with equipment vendors is a credibility signal. Packaging technology, in particular, has become a key competitive battleground: TSMC's SoIC and CoWoS platforms and AMD's use of chiplet architectures have raised the bar for what foundry customers expect in 3D integration.

Neither company disclosed financial terms for the collaboration, milestone targets or a timeline for when jointly developed technologies might reach volume production. The announcement carries forward-looking-statement caveats that are standard for listed US companies but are worth noting given the aspirational language used throughout the release.