AnalogAI licenses SST memBrain SAGE IP for sub-watt edge AI chips

AnalogAI will use Microchip's analog compute-in-memory IP to build processors that train and run inference on robots, drones and vehicles below one

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AnalogAI, a South Korean edge AI processor startup, has licensed the memBrain Synaptic Analog Generative Engine (SAGE) intellectual property from Silicon Storage Technology (SST), a wholly owned subsidiary of Microchip Technology (NASDAQ: MCHP). The agreement positions SST's analog compute-in-memory technology as the core inference engine inside AnalogAI's first commercial processors, which are designed for physical-world applications including humanoid robots, autonomous drones and vehicles.

The key technical proposition is power efficiency: AnalogAI says its processors will deliver high levels of analog compute-in-memory (aCIM) performance at or below one watt. That constraint is especially relevant for battery-dependent or thermally limited form factors where conventional digital inference accelerators are impractical. Unlike most edge AI silicon, which handles inference only after a model has been trained elsewhere, AnalogAI's architecture is designed to perform on-device training and inference simultaneously, enabling real-time adaptation to changing environments after deployment.

The technology

SST's memBrain SAGE IP is built on the company's SuperFlash non-volatile memory technology and has been validated in 40 nm and 28 nm foundry processes, with a 22 nm node roadmap under development. The IP block includes a Tensor In-Memory Logic Element (TILE), a proprietary bitcell capable of storing up to eight bits per cell at nanoamp operating levels, alongside custom array decoders, optimised digital-to-analogue and analogue-to-digital converters, and summator circuitry. SST packages the IP with integration support and simulation models, reducing the development overhead for a fabless customer such as AnalogAI.

Jaejun Lee, AnalogAI's chief executive, said the company conducted a broad survey of available aCIM IP before selecting SST's offering, citing the silicon-proven status of memBrain SAGE as a key factor in accelerating its own development timeline. Mark Reiten, senior vice president of Microchip's Intelligent Compute business unit, described AnalogAI as the newest member of a "rapidly expanding ecosystem" of memBrain licensees, though Microchip did not disclose how many licensees the programme currently holds, nor the financial terms of the agreement.

Market context

Analog compute-in-memory is an increasingly active corner of the edge AI silicon market, drawing interest from both established chipmakers and well-funded startups. The appeal is straightforward: by performing multiply-accumulate operations directly within the memory array, aCIM architectures avoid the energy cost of repeatedly shuttling data between separate compute and memory blocks, a bottleneck that limits conventional digital designs at the edge.

Competition in ultra-low-power edge inference spans a range of approaches. Digital neural processing units from Arm, Syntiant and Eta Compute address some of the same markets; memristive and phase-change memory approaches are in various stages of commercialisation at research and early-product level. The distinct angle AnalogAI is pursuing, combining on-device training with inference in a single low-power design, is less common in commercial silicon and, if validated at scale, could differentiate its processors in applications such as adaptive robotics where the environment changes faster than a cloud retraining loop can respond.

Regulatory tailwinds are also relevant. The EU AI Act's provisions for high-risk autonomous systems, including robotics and certain vehicle applications, will require demonstrable robustness under distribution shift. Hardware that adapts on-device rather than relying on periodic cloud-based retraining may offer a compliance-relevant argument to enterprise buyers in those categories.

AnalogAI has not disclosed a product launch date, customer names, or pricing for its processors. The immediate milestones for observers to watch are a tape-out announcement on the 28 nm node and any named design-win customers in the robotics or autonomous vehicle supply chain.