STMicroelectronics and NUS launch HELIX edge AI lab in Singapore
STMicroelectronics and the National University of Singapore (NUS) have jointly launched the ST-NUS HELIX Corporate Lab, a four-year research initiative targeting the next generation of edge AI silicon. HELIX, an acronym for Hardware for Embodied Low-power Intelligent Xcceleration, is hosted at NUS's College of Design and Engineering and School of Computing, and is backed under Singapore's Research, Innovation and Enterprise 2025 (RIE2025) national funding plan.
The programme centres on memory-centric processor architectures, in-memory computing, and scalable compute-and-memory integration. ST will provide NUS researchers with a dedicated design chassis built on its proprietary P18 18nm Fully Depleted Silicon On Insulator (FD-SOI) process, combined with embedded Phase Change Memory (PCM). FD-SOI allows ultra-low-power operation and adaptive body-biasing; PCM delivers dense, non-volatile on-die storage alongside conventional SRAM. Together, ST says, the combination can significantly cut the off-chip data movement that dominates energy consumption in memory-bound AI workloads.
The research agenda
HELIX's technical scope spans the full stack: AI model design, system architecture, heterogeneous accelerators, on-chip memory hierarchies, circuit design, chip integration, and silicon implementation. A particular focus is embodied AI, where inference runs directly inside a physical form such as a robot, drone, or humanoid device. That category demands real-time multi-modal sensing and actuation under tight power budgets, conditions that cloud-offload approaches cannot reliably meet.
Laurent Malier, Executive Vice President for Global Technology R&D at STMicroelectronics, said: "Through HELIX, we are creating an industrially relevant foundation to explore differentiated AI computing technologies and accelerate the translation of promising research into scalable semiconductor solutions." NUS President Professor Tan Eng Chye framed the lab as a vehicle for building both hardware capability and a talent pipeline for Singapore's semiconductor and AI industries.
The launch was officiated by Ms Low Yen Ling, Senior Minister of State for Trade and Industry, a signal of the strategic weight Singapore's government places on the initiative.
Market and competitive context
Edge AI silicon is one of the most active areas of semiconductor R&D globally. ST competes with Qualcomm, NXP, Nordic Semiconductor, and a crop of well-funded fabless startups building purpose-built inference chips for IoT, robotics, and automotive applications. The HELIX lab gives ST a structured academic partner for exploratory research it would be costly to fund entirely in-house, while NUS gains access to an industrial-grade design environment that typically sits behind corporate firewalls.
Singapore's position in this race is deliberate. The city-state has invested heavily in semiconductor and AI infrastructure as part of its Smart Nation agenda, and RIE2025 allocates significant grants to exactly this kind of industry-anchored corporate lab model. Several global chip firms, including Micron and GlobalFoundries, operate manufacturing and R&D facilities in Singapore, giving ST a dense local ecosystem to draw on.
The memory-centric architecture emphasis is also timely. As foundation models push toward on-device deployment, the bandwidth bottleneck between compute and memory is increasingly the binding constraint on edge performance. In-memory computing approaches, which perform arithmetic directly within memory arrays, are attracting attention from researchers and investors as a potential route around that bottleneck, though commercial silicon implementations remain early-stage across the industry.
HELIX's four-year timeframe positions its outputs alongside the next wave of edge AI product cycles. ST has indicated that research outputs will feed into its broader product and IP pipeline, with talent development an explicit secondary objective. The lab's first demonstration milestones have not yet been publicly disclosed.