GlobalFoundries and RAAAM tape out GCRAM chip on FDX platform

The partners report a 40% memory area shrink and up to 60% power reduction versus SRAM, with lead-customer access planned for early 2027.

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GlobalFoundries (GF) and Israeli fabless IP firm RAAAM Memory Technologies have announced a joint development agreement to bring Gain-Cell RAM (GCRAM) technology to production readiness, marking the milestone with a successful tape-out of a GCRAM test vehicle on GF's FDX fully-depleted silicon-on-insulator (FD-SOI) platform. The two companies say the co-designed bitcell achieves a 40% reduction in memory area and up to 60% lower memory power consumption compared with conventional SRAM, using what they describe as "pushed" design rules on the FDX node.

The partnership is targeting lead-customer design access in early 2027. NXP Semiconductors, which develops embedded processing for automotive and industrial edge applications, said it is actively evaluating the GCRAM solution, lending the announcement its first named third-party validator.

The technology case

On-chip memory has become one of the most area- and power-constrained components in modern SoCs, particularly as edge AI workloads demand local inference without the latency or energy cost of off-chip data movement. SRAM, the incumbent technology, scales poorly below advanced nodes and consumes disproportionate silicon real estate.

RAAAM's GCRAM is a gain-cell architecture, in which each bitcell uses a transistor-based read path that amplifies the stored signal, enabling smaller cells and lower leakage. The company says the technology is compatible with standard CMOS flows, meaning it can in principle substitute for SRAM in existing design methodologies without a full process migration. Robert Giterman, CEO and co-founder of RAAAM, said the ultra-low leakage of GF's FD-SOI platform extends data-retention characteristics, which he argues enables meaningful energy savings for edge AI devices.

Victor Wang, vice president of front-end innovation at NXP Semiconductors, said the industry requires "a paradigm shift in on-chip memory" and described the projected area and power improvements as offering "a clear path to increasing on-chip memory capacities." NXP's involvement is notable given the company's broad footprint in automotive-grade and industrial-edge silicon, markets where power budgets are tightly constrained.

Market and competitive context

The embedded non-volatile and embedded SRAM replacement market has attracted several competing approaches in recent years. Emerging bitcell architectures, including 3T gain-cell variants and ferroelectric RAM (FeRAM), are being evaluated alongside more incremental SRAM optimisations from major IP providers such as ARM and Synopsys. At the foundry level, TSMC and Samsung have their own FD-SOI-adjacent programmes, though GF has maintained a differentiated position in the FD-SOI segment, particularly for low-power and automotive customers in Europe and the United States.

GF's decision to deepen its IP portfolio on FDX by co-developing with a specialist IP company like RAAAM reflects a broader industry trend: foundries moving beyond pure wafer capacity to offer integrated design-IP bundles that reduce time-to-tapeout for fabless customers. Sudipto Bose, GF's vice president of FD-SOI product management, framed the collaboration as part of a continuing effort to "redefine the power-performance-area equation" for AI and other advanced applications.

The test chip tape-out represents a pre-qualification milestone. The commercial case will be tested in 2027 when lead customers receive design access and can benchmark GCRAM under real SoC conditions. Investors and ecosystem partners will be watching for published silicon characterisation data, yield figures, and the conversion of NXP's evaluation into a committed design win as the key near-term signals of commercial viability.