Microchip Technology launches timing module for AI and 5G
Microchip Technology has launched the MD-990-0011-B family of plug-in timing modules, designed to deliver high-precision synchronisation for data-centre servers and 5G virtualised Radio Access Networks (vRAN). Developed in collaboration with Intel, the modules are built for compatibility with Intel Xeon 6 SoC-powered server platforms and are available in production quantities as of 23 April 2026.
The product comes in two variants — the MD-990-0011-BA01, offering four hours of holdover performance, and the MD-990-0011-BC01, which extends that to eight hours. Holdover refers to a module's ability to maintain accurate timing during GNSS outages or network disruptions, a capability critical for always-on infrastructure. The modules support automatic source selection and locking across Global Navigation Satellite Systems (GNSS), Synchronous Ethernet (SyncE) and Precision Time Protocol (PTP), consolidating multiple discrete timing components into a single plug-in unit.
What is in the module
Key integrated components include the ZL80132B SyncE synthesiser, which provides two independent Digital Phase-Locked Loop (DPLL) channels, alongside Oven Controlled Crystal Oscillators (OCXOs) rated for up to eight hours of holdover. Supporting components include a MCP9808 temperature sensor, a 24LC024 EEPROM for board configuration, and a VC-820 oscillator for low-jitter performance. Microchip says this level of integration reduces design complexity for OEMs and ODMs, shortens time-to-market, and simplifies supply-chain management.
Randy Brudzinski, corporate vice president of Microchip's frequency and time systems business unit, said the module "eliminates the complexity of custom timing circuits, providing integration and reliability, accelerating innovation and reducing time-to-market for data centres and 5G networks."
Mike Merluzzi, GM of radio access networks at Intel, added that the module aligns with Intel's platform strategy for 5G, AI and cloud computing by simplifying timing integration on Xeon 6-based systems.
Market context
Precision timing is a growing pressure point in the data-centre sector as distributed AI workloads and disaggregated radio architectures demand sub-microsecond synchronisation across large server clusters. A mistimed cluster can degrade inference throughput or introduce phase errors in vRAN deployments, making robust holdover a commercial differentiator rather than a background technical detail.
Microchip competes in this space against dedicated timing-IC vendors such as Renesas (which acquired Integrated Device Technology) and Silicon Laboratories, as well as internal timing designs from hyperscale operators. Its claimed advantage is a vertically integrated portfolio stretching from oscillator components to complete timing systems — a heritage the company attributes to over 75 years of frequency and timing engineering. Whether a plug-in module at this level of integration undercuts the total cost of ownership versus a custom board design will depend on OEM volumes and the pace of vRAN rollout by mobile operators.
From a standards perspective, the module's PTP support aligns with ITU-T G.8275.1 and G.8275.2 profiles, which are the predominant timing standards for mobile fronthaul and backhaul. As telecoms operators in Europe progress NIS2 compliance and infrastructure resilience requirements, the ability to demonstrate verified holdover performance during GNSS signal loss is increasingly a procurement criterion rather than a bonus feature. Microchip has not disclosed whether the module carries any third-party certification against these profiles, which enterprise buyers and network operators are likely to ask about before committing to volume deployments.