Microchip and Micron demo PCIe Gen 6 storage fabric for AI data centres

Microchip Technology and Micron Technology have jointly demonstrated an end-to-end PCIe Gen 6 storage architecture at the 2026 Future of Memory and Storage (FMS) Conference. The proof-of-concept pairs Microchip's Switchtec Gen 6 PCIe fanout switch with Micron's 9650 NVMe SSDs to form a high-bandwidth, low-latency storage fabric aimed at AI training, high-performance computing (HPC) and cloud data centre infrastructure.

The architecture is designed around composable, disaggregated system topologies that allow data centre architects to scale storage independently from compute. Microchip says its Switchtec switch, fabricated on a 3 nm process, supports high lane counts, multicast data distribution, advanced error containment and a hardware root of trust with post-quantum-safe cryptographic algorithms meeting CNSA 2.0 standards. The Micron 9650 is described by the company as the first mass-produced PCIe Gen 6 SSD and is positioned for data-intensive workloads requiring sustained IOPS and low latency.

Brian McCarson, corporate vice president and general manager of Microchip's data centre solutions business unit, said the collaboration reflects the need for a cohesive systems approach: "We're bringing together complementary strengths in switching and storage to demonstrate how a well-aligned ecosystem can enable scalable, high-bandwidth architectures for next-generation AI and cloud platforms."

The technology case

PCIe 6.0 doubles the per-lane transfer rate of PCIe 5.0, moving from 32 GT/s to 64 GT/s. For AI infrastructure, where training and inference runs must shuttle large model weights and activation data between accelerators and storage at high speed, this additional headroom matters. The standard also introduces pulse-amplitude modulation 4 (PAM4) signalling and forward error correction, which adds complexity at the physical layer but allows the bandwidth gain without proportionally increasing lane counts or power draw.

Larry Hart, senior director of solutions marketing for Micron's core data centre business unit, framed the joint demonstration as an interoperability signal: storage performance and ecosystem alignment must advance together, he said, rather than components being optimised in isolation.

Market context

PCIe Gen 6 adoption is still early. The PCI-SIG finalised the Gen 6 base specification in 2022, but volume production of compliant switches and SSDs has been limited; Micron's claim of being first to mass-produce a Gen 6 NVMe SSD, if accurate, places it ahead of several storage competitors still qualifying Gen 5 products. Microchip competes in the PCIe switch segment against Broadcom, whose PEX series is well-entrenched in hyperscaler rack designs, and a smaller number of emerging players targeting disaggregated Compute Express Link (CXL) fabrics.

For data centre buyers, the composable storage angle is increasingly relevant. Disaggregated architectures are gaining traction in AI cluster designs where GPU utilisation rates are a key cost variable; decoupling storage from fixed server configurations allows capacity to be reallocated across workloads without hardware changes.

The post-quantum cryptographic capability built into the Switchtec switch is worth noting separately. CNSA 2.0 is the US National Security Agency's recommended cryptographic suite for national security systems, and its inclusion in a commercial data centre switch suggests Microchip is targeting sovereign and defence-adjacent infrastructure customers as well as commercial hyperscalers.

Standards and regulatory read-across

The FMS demonstration is a pre-commercial showcase; neither Microchip nor Micron disclosed design wins, customer commitments, pricing or volume availability timelines. Broader PCIe Gen 6 ecosystem readiness, including host CPU and GPU controller support from AMD and Intel, will determine how quickly the architecture moves from conference demonstration to production deployment. Observers will also watch whether CXL 3.x, which sits atop PCIe Gen 6, accelerates memory pooling use cases that further justify the bandwidth upgrade in AI rack architectures.