Microchip releases VectorBlox 3.0 SDK for FPGA edge AI inference
Microchip Technology has released VectorBlox 3.0, an updated software development kit designed to simplify the deployment of convolutional neural network models on its PolarFire FPGA and SoC platforms. Available at no charge, the SDK is aimed at engineers building AI inference pipelines in power-constrained and mission-critical environments, including aerospace, defence, space and industrial edge systems.
The headline technical addition in version 3.0 is sparsity-based model compression, a technique Microchip attributes to its earlier acquisition of Neuronix. By skipping zero-valued operations in sparse neural networks, the toolchain is said to reduce compute and memory requirements while preserving model accuracy. The company says this allows developers to run multiple vision or sensor-based AI workloads on a single low-power device rather than dedicating separate silicon to each function.
Aerospace and space validation
Two named customers provided quotes alongside the release, lending the announcement unusual operational specificity for a developer-tools launch. Planetek Italia's SPACEDGE services line manager Vito Fortunato said VectorBlox had been used to deploy onboard AI pipelines on the AI-eXpress-1 satellite, launched in 2025, supporting real-time Earth observation tasks including object detection and semantic scene analysis. The PolarFire platform's single-event-upset immunity, which protects against bit-flips caused by cosmic radiation, was cited as a key requirement for continuous low-Earth-orbit operations.
AIKO, a space autonomy company, said it validated the PolarFire SoC and VectorBlox combination for its clear_CHARLES suite, which performs onboard cloud and ship detection for adaptive payload operations. Federico Fontana, head of hardware engineering at AIKO, described the combination as enabling "increasingly autonomous, responsive and software-defined space systems." Microchip also highlighted the Spacecraft Pose Network v2 neural network, which runs on PolarFire hardware and is designed for autonomous rendezvous, docking and debris-removal applications.
VectorBlox 3.0 integrates with Microchip's existing Libero SoC Design Suite and CoreVectorBlox IP, and the company is hosting a webinar on 16 July 2026 covering the CNN inference performance claims in more detail.
Market context
FPGA-based edge inference occupies a distinct niche in the AI hardware landscape. Unlike GPU-centric cloud or on-premises inference, FPGAs offer deterministic latency, low idle power, and the radiation-hardened variants required in space and defence applications. Microchip competes in this space against Intel (whose Altera division produces the Agilex and Stratix families) and AMD (Xilinx), both of which have their own AI inference IP and toolchain ecosystems. Lattice Semiconductor addresses the lower-power end of the market with its sensAI stack.
The release of a free SDK is a deliberate developer-acquisition move in a market where toolchain friction is frequently cited as a barrier to FPGA adoption. Engineers accustomed to PyTorch or TensorFlow workflows have historically found FPGA design flows steep; integrated compilation and deployment pipelines that accept standard CNN model formats directly reduce that friction.
Regulatory and export context
Aerospace and defence applications of AI inference are subject to increasingly close scrutiny under US export-control regimes administered by the Bureau of Industry and Security. Radiation-hardened and SEU-immune FPGAs are controlled items, and the specific use cases highlighted in the release, including autonomous satellite proximity operations and onboard defence payloads, sit squarely in categories that attract EAR and potentially ITAR review. Customers outside the US will need to confirm appropriate export licences before deploying PolarFire-based systems in classified or dual-use programmes. Microchip did not address export-control considerations in its release.